A MEMS Clearinghouse® and information portal
for the MEMS and Nanotechnology community
RegisterSign-In
MEMSnet Home About Us What is MEMS? Beginner's Guide Discussion Groups Advertise Here
News
MEMSnet Home: MEMS-Talk: Mask size
Mask size
2003-07-16
Tom Fan
2003-07-16
David Nemeth
2003-07-16
Dennis Baird (2 parts)
2003-07-17
Marcus
2003-07-16
Michael D Martin
2003-07-17
Werner J. Karl
2003-07-17
Hornung, Michael
Mask size
Hornung, Michael
2003-07-17
Hi Tom,

the mask must hold somewhere. Most maskaligner hold the mask with vacuum,
either from top or bottom. If the mask is hold from bottom (chrome side) the
maximum wafer size depends on the opening of the mask holder. If the mask is
hold from the top the wafer size can be the same as the mask. However, the
exposure area is limited by the opening of the mask holder.

Moreover, in case of vacuum contact exposure mode, the edge of 1/2" on the
mask is necessary to seal the vacuum chamber.

Therefore a 1" larger mask is recommended usually. If existing masks should
be used with wafers of the same size, the manufacturer of your maskaligner
may find a solution for that. However, this will not be a standard solution.

        Michael.


        Dr. Michael Hornung
        Application Engineer
        ----------------------------------------------------------------
        SUSS MicroTec
        Berliner Str. 48 / D-35614 Asslar
        Phone:  +49-(0)6441-984152
        FAX:            +49-(0)6441-98418852
        e-mail: [email protected]
        ----------------------------------------------------------------



-----Ursprüngliche Nachricht-----
Von: Tom Fan [mailto:[email protected]]
Gesendet: Mittwoch, 16. Juli 2003 07:27
An: [email protected]
Betreff: [mems-talk] Mask size



Hi all,

Whats the typical correlation between the sizes of photomasks and wafers in
MEMS fabrication? If I were to fabricate microdevices on 4" wafers, do I
need
4" or 5" photomasks? I learned from an Internet site that the masks should
be
1" larger than the wafers to be used. Is this customary or masks of the same

size as wafers can also be used? Anybody can clarify this issue for me?

Thanks,
Tom Fan


_______________________________________________
[email protected] mailing list: to unsubscribe or change your list
options, visit http://mail.mems-exchange.org/mailman/listinfo/mems-talk
Hosted by the MEMS Exchange, providers of MEMS processing services.
Visit us at http://www.memsnet.org/

reply
Events
Glossary
Materials
Links
MEMS-talk
Terms of Use | Contact Us | Search
MEMS Exchange
MEMS Industry Group
Coventor
Harrick Plasma
Tanner EDA
Nano-Master, Inc.
Harrick Plasma, Inc.
MEMStaff Inc.
Mentor Graphics Corporation