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MEMSnet Home: MEMS-Talk: RIE reflected power too high during Si etch
RIE reflected power too high during Si etch
2004-01-06
Michael L
2004-01-07
R. Brent Garber (2 parts)
2004-01-07
Neal Ricks
2004-01-07
Tony Li
2004-01-06
[email protected]
RIE reflected power too high during Si etch
Neal Ricks
2004-01-07
Michael,
If your system is a capacitively coupled, parallel plate, RIE, the impedence of
the plasma has a lot to do with the coupling of the power, and the matching
component required from the tuning network.  If you are using a standard SF6/O2
recipe, the gas can be tough to break down, and adding a little Helium can
assist in achieving a more efficient ionization.

Once source for more info. is Plasma Etching; An Introduction, by Manos and
Flamm.

Regards,
Neal


Michael L  wrote:
Hello,

I am trying to isotropically etch grooves (20 um wide; 10-20 um deep) in Si
using an RIE. I am getting high reflected powers whenever I deviate from the
standard (anisotropic) Si etch recipe. Sometimes, the value starts off low
but then reaches 10% of the forward power, at which point the system cuts
off automatically. Would anyone have any information (or know where I can
get some information) on the main factors that affect the reflected power?

Any information would be useful.

Many thanks,

Michael

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