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MEMSnet Home: MEMS-Talk: Si02/Si3N4 membranes
Si02/Si3N4 membranes
2005-01-10
[email protected]
2005-01-10
Yanjun Tang
2005-01-10
Michael D Martin
2005-01-10
Altena, G. (Geert)
Si3N4/SiO2 membranes
2005-01-11
[email protected]
2005-01-10
Mattes, Mike
Si02/Si3N4 membranes
Altena, G. (Geert)
2005-01-10
Hi,

> I am trying to etch SiO2/Si3N4 membranes in 100 Si wafer.
> The thickness of the Si3N4 and thermal oxide layers are
> 100nm and  2.5micron, respectively.

Is this your layerstack? Nitride on top?

Si3N4
SiO2
Si

> The Si3N4 layer is removed by the  RIE ,  while  SiO2 in BHF
> and then etched in KOH to produce the window membrane.
> Unfortunately,  each time I repeat my process the membranes brake.
>  Could someone  advise me why this is happening and suggest
> solution to this problem.

I assume here that the Si02 and Si3N4 layers are both on the topside and
bottomside of the wafer and that you etch holes in the layers on one
side to get the membranes on the other side.

Most likely, the mebranes break due to the compressive stess in the
oxide layer. Perhaps you can etch holes top-nitride layer with RIE and
then etch the underlying oxide away with BHF.

Regards,
\Geert.
--
Geert Altena  -<=>- Integrated Optical
MicroSystems
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