Hi everybody!


 We are having from time to time after silicon nitride plasma-etch(NF3
 plasma) som rests on the sides of the poly gate of P-chanal CMOS. The
 gate and poly thicknesses are 650Å and 5000Å respectively. The nitride
 is deposited on an oxide (SiO2) which has a thickness of ca 550Å. The
 Si-nitride thickness is ca 1600Å. We plasma etch the Si3N4  in NF3 for
 40 s. We implant the source and drain (Bor). The implant is followed
 with an oxidation (SiO2) ca 3900Å. Then we strip the silicon nitride.
 The rests of the Si-nitride on the poly gate sides are living behind
 them open areas, which are subject to the n+ doping(gate contact). This
 has an effect of decreasing the channel conductance(lowers the
threshold
 voltage of the P-channel CMOS).

 I greatly appreciate any help of any kind
 The process we have is a DMOS(DOUBLE DIFFUSION)PROCESS.

 Best regards Atmane.