Dear Yang,

It looks like I am dealing with the same kind of process: SOI wafers
with device layer of 340 nm, and backside etching of handle layer with
TMAH (25wt%, 90C).

I am currently using a multilayer of PECVD oxides and nitrides as etch
mask. In order to enhance the masking properties of these layers, you
can anneal them at high temperature (> 800C) for at least 20 minutes in
nitrogen atmosphere.

Furthermore, I use a stainless steel holder to protect the frontside of
the wafer.

Hope this can help,

Regards,

Massimiliano Decarli


> Dear all,
>
> Thank you for your reply. The top Si layer of SOI is only 300 nm and with
> pattern, therefore I could not grow thermal SiO2 on top. For my purpose, one
> way is to put a glass substrate on top side of SOI and seal the edge with
> some polymer. I don't know wheather there is such kind of polymer which can
> suvive in base (KOH or TMAH) and be easy to remove afterwards.
>
> Regards
>
> Weiquan Yang
> EE department, University of Texas at Arlington

Massimiliano Decarli

BioMEMS Group
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