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MEMSnet Home: MEMS-Talk: DRIE problem in etching high resistivity silicon substrate
DRIE problem in etching high resistivity silicon substrate
2010-09-14
[email protected]
2010-09-14
Robert Ditizio
2010-09-15
Ned Flanders
DRIE problem in etching high resistivity silicon substrate
Robert Ditizio
2010-09-14
Dayong:

Are you using an electrostatic clamp?  If so, the high resisitivity wafers
may not be clamping properly leading to excessive heating, and undercut of
the mask.

Robert

On Mon, Sep 13, 2010 at 5:42 PM,  wrote:

> Hi everyone ,
>
>        We are now etching holes through silicon wafers. When we are using
> low resistivity silicon wafers, the sidewall profile can be perfectly
> controlled, but when using high resistivity silicon wafers, very serious
> undercut was observed at a depth only about 50 micron when Al was used as
> etching mask. So, is this phenomenon caused by the charge accumulation due
> to the high resisitivity or anything else? Anybody has experienced this and
> has a solution? Thanks.
reply
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