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Hitesh Sahoo's Resume

Contact249 South 44 Street
Apt 2F
Philadelphia, PA 19104
US
215-915-3379
[email protected]
GoalEntry level jobs in the field of MEMS design
SkillsCOMSOL, MATLAB, LabVIEW, CClean room experience
QualificationsEDUCATIONAL QUALIFICATION
University of Pennsylvania, Philadelphia, PA, USA May 2013
Master of Science in Engineering in Nanotechnology CGPA: 3.75/4
Coursework: Introduction to MEMS/NEMS | Principles of Micro-fabrication Technology| Nano-scale Science & Engineering | Fabrication & Characterization of Nano Devices | Atomistic Modeling in Materials Science | Quantum Mechanics-I | Finite Element Analysis & Applications | Drug discovery and development

Birla Institute of Technology and Science – Pilani, India 2011
Bachelor of Engineering (Honors) in Electronics and Instrumentation CGPA: 8.55/10


TECHNICAL SKILLS
Programming Languages: C,C++, FORTRAN, VHDL, HTML
Software: MATLAB, LabVIEW, COMSOL, AutoCAD, PSPICE, PSoC, TCAD, PineChem, MS Excel, MS Powerpoint
Equipments used: Powder X-Ray Diffractometer, Spinner, Mask aligner, Biopotentiostat
Cleanroom experience for micro-fabrication (Wolf Nanofabrication Facility, University of Pennsylvania)

EXPERIENCE
Research Assistant, Prof. Kevin Turner’s Team, University of Pennsylvania [Jan 2013 - Present]
Modeled a 2D scanning MEMS structure on COMSOL to be used for an optical device.
Currently working on the fabrication of the MEMS structure using micro-transfer printing.

Research Assistant, Prof. Jorge J Santiago-Aviles’s Team, University of Pennsylvania [Jan 2012 – Dec 2012]
Designed and optimized the faradaic component of the super-capacitor, using ProDOT (a thiophene based conducting polymer) to reach a capacitance of 110 F/g. Achieved energy and power density of 60Wh/kg and 800kW/kg respectively
(Paper published at Journal of Physics: Conference Series.)

Teaching Assistant at Detkin Lab, University of Pennsylvania [Sept 2011 – Dec 2011]
Designed lab experiments based on LabVIEW and mentored a team on their Senior Design project.

ST Ericsson, Bangalore, India [Internship] [Jan 2011 – June 2011]
Worked in the 3GPP Telephony team for the following two projects:
Reduced the test time by 90% for AT Commands by developing an automatic test suite.
Simulated 60 test cases (approx.) to test and reduce the errors to 1% in the OEM module.
Worked on several hardware issues raised by clients (Samsung, HTC) for ST Ericsson.


CONFERENCE
Design of a beam based NEMS memory element on the lines of ITRS projections for Nano-mechanical memory
elements, using the concept of static charge storage. - Presented at Tech Connect World Conference (Microtech) 2012.
Designed an energy optimized (100nW per read-and-write cycle) memory element using principles of electrostatic actuation.Optimized the read-and-write time to 100 nano-seconds (approx.) for an under-damped system.


LEADERSHIP EXPERIENCE
Worked in the core team of IEEE Student Chapter at BITS-Pilani and organized a national level workshop on VLSI
having a participation of over 70 including students and industry professionals.

As the publicity head for Urja (A BITS Community initiative for energy conservation), increased awareness leading to
a 10% reduction in electricity consumption of the campus.
Updated: 2013-05-20
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