For example glasses which have to be combined with a silicon wafer (wafer bonding or FC) require a CTE of around 3.2 ppm K -1 to avoid a CTE mismatch. Glass wafers are fully compatible to WLP-Lines. There is no difference between processing Si-Wafers ...
The new Firefly inspection and metrology system has been designed to detect defects smaller than one micron in multiple applications, including: fan-out wafer level packaging (FOWLP), CMOS image sensors, microelectromechanical systems (MEMS) and radio ...
Ultra-thin, alternating layers of neodymium titanium oxide ... into how changes in composition brought about by both environmental factors and film growth processing conditions were effecting the electronic environment surrounding the titanium atoms.
Taiwan-based United Microelectronics (UMC) has announced it is teaming up with dedicated MEMS foundry Asia Pacific Microsystems (APM) to provide enhanced MEMS manufacturing services for mutual customers. UMC will leverage its 8- and 12-inch production ...
senior director of integrated interconnect and packaging technology at TSMC, as saying. SEMI believes that semiconductor fab equipment spending will gain momentum through the end of 2016. For 2017, 13% growth is forecast. Activity in the 3D NAND ...
